/*
 * Copyright 2024 ywcai
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *      http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */

`include "defines.v"
`timescale 1ns/1ps

module if_id(
	input	wire				clk,
	input	wire				rst_n,

	input	wire[`MemAddrBus]	pc_i,
	input	wire[`InstDataBus]	inst_i,
	input	wire				stall_id_req_i,
	input	wire				flush_id_req_i,

	output	reg[`MemAddrBus]	pc_o,
	output	reg[`InstDataBus]	inst_o
	);

	always @(posedge clk) begin
		if (rst_n == `RESET_ENABLE || flush_id_req_i) begin
			pc_o <= `ZERO_ADDR;
			inst_o <= `INST_NOP;
		end else if(!stall_id_req_i) begin
			pc_o <= pc_i;
			inst_o <= inst_i;
		end
	end
	
endmodule
